1 S8301 hd-sdi data retimer december 8, 1998 / revision a S8301 hd-sdi data retimer ? features ? hd-sdi retimer ? 1.485 gbps operation ? lock detect ? port bypass ? +3.3v power supply ? smpte 292m compliant ? 32 pin tqfp applications ? routers ? distribution amplifiers ? backplanes device specification general description the hd-sdi (high definition serial digital interface) retimer circuit is used in full-speed (1.485 gb/s) hdtv bit stream switching and distribution systems. it contains a monolithic clock recovery unit (cru), a lock detect feature and a port bypass circuit. the cru may be used alone to implement a general purpose repeater needed for applications where a re-timed and buffered signal is required. the data retimer performs the function of a port bypass cir- cuit followed by a clock and data retiming phase locked loop (cdr). the cdr re-times incoming se- rial data, detects whether a valid signal is present and outputs a low jitter serial data stream. serial data out serial data out coax or fibre dr dr S8301 S8301 crosspoint switch s2025 S8301 S8301 serial data in serial data in coax or fibre video router figure 1. system block diagram
2 hd-sdi data retimer S8301 december 8, 1998 / revision a overview the data retimer performs two functions. the first is to perform the function of a port bypass circuit for nodes in a multi-rate switch or router. the low jitter accumula- tion of the port bypass path is essential in these sys- tems. the second function is to retime and restore signal quality after transmission and equalization. the low jitter transfer peaking and the high jitter tolerance specifications of the clock and data recovery pll are essential in these applications. in addition, the lock detect circuit monitors the incoming signals for run length, transition density and frequency. the output of this circuit is useful for link performance monitoring and detection of channel present. jitter performance the data retimer complies with the minimum jitter tol- erance requirements proposed by smpte 292m when used with differential inputs and outputs. in addition, the data retimer is designed for minimum jitter generation and jitter transfer specifications. this allows the opti- mum system design for arbitrated loop architectures. jitter tolerance input jitter tolerance is defined as the amplitude of frequency dependent, random and deterministic jitter that causes the clock recovery pll to violate the ber specifications. alignment jitter the variation in position of a signal's transitions rela- tive to those of a clock extracted from that signal. the bandwidth of the clock extraction process determines the low-frequency limit for alignment jitter. alignment jitter is out of band with respect to the pll bandwidth. timing jitter the variation in a position of a signal's transitions occuring at a rate greater than a specified frequency, typically 10 hz. variations occuring below this speci- fied frequency are termed wander and are not ad- dressed by this practice. timing jitter is in band with respect to the pll bandwidth. deterministic jitter tolerance deterministic jitter tolerance is the amount of deter- ministic jitter that the clock recovery pll must tolerate. lock detect the data retimer lock detect circuit monitors the selected input signal to detect the presence of the channel. this is done by monitoring the run length, transition density and frequency content of the in- coming data. the frequency monitor circuit checks the difference between the divided down recovered clock and the externally supplied reference clock (refclk). if the frequency difference of the recov- ered clock and the reference clock varies by more than 240 ppm the part will be declared out of lock. in the out of lock state the pll will lock to the local reference clock and periodically poll the serial data inputs looking for data with valid frequency content. the lock detect output transitions to a logic 1 when the pll is locked to data, and transitions to a logic 0 when locked to the reference clock. valid data datap/n or altp/n lockdet figure 3. lockdet function figure 2. functional block diagram phase detect loop filter freq detect run length detect divide by 20 vco refclk altp/n datap/n sel lockdet doutp/n bpssp/n hdtv clock and data retimer dq m u x ck lock2ref
3 S8301 hd-sdi data retimer december 8, 1998 / revision a e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p t u o d n t u o d . f f i d l c e p v l o4 5 k c o l c e h t y b d e m i t e r n e e b s a h t u p t u o s i h t . a t a d t u p t u o l a i r e s t n e r r u c s a i b a m 0 2 - 4 1 ( r e t t i m e n e p o . l l p y r e v o c e r a t a d d n a . ) d e d e e n p a t a d n a t a d . f f i d l c e p v l i1 2 . l c e p v l l a i t n e r e f f i d . a t a d t u p n i l a i r e s n t l a p t l a . f f i d l c e p v l i8 2 9 2 f i 9 e r u g i f e e s . l c e p v l l a i t n e r e f f i d . a t a d t u p n i l a i r e s e t a n r e t l a . d e s u t o n k l c f e rl t ti2 2g n i s i r , z h m 5 2 . 4 7 t a y l l a n i m o n , l l p e h t r o f k c o l c e c n e r e f e r . g n i s a i b k c o l c e c n e r e f e r r o f 0 1 e r u g i f e e s . e v i t c a e g d e 1 f p l 2 f p l g o l a n a2 1 1 1 7 2 o t 2 f p l . s n i p r o t i c a p a c r e t l i f p o o l w n i f 2 . 2 h t i w s e i r e s n i 7 2 h t i w s e i r e s w . 8 e r u g i f e e s . 2 f p l o t n f e r k c le t a t s 3 l t t i4 2e h t o t k c o l o t d e c r o f e b l l i w l l p r d c e h t e v i t c a n e h w . w o l e v i t c a a t a d e h t , d e t c e n n o c s i d n e h w . ) k l c f e r ( k c o l c e c n e r e f e r l a c o l r o f d e s s a p y b e b l l i w l l p e h t d n a e d o m t s e t o t n i t u p e b l l i w r e m i t e r . g n i t s e t y r o t c a f t e d k c o ll t to7 1s i l l p r d c e h t s e t a c i d n i t e d k c o l , e v i t c a n e h w . h g i h e v i t c a l l i w l l p r d c e h t , e v i t c a n i n e h w . m a e r t s a t a d l a i r e s e h t o t d e k c o l . n o i t i d n o c a t a d f o s s o l a g n i t a c i d n i k c o l c e c n e r e f e r l a c o l e h t o t k c o l p s s p b n s s p b . f f i d l c e p v l o0 2 9 1 . t u p t u o s s a p y b t r o p l e sl t ti0 3, w o l s i l e s n e h w . d e t c e l e s s i n / p t l a , h g i h s i l e s n e h w . d e t c e l e s s i n / p a t a d l e s f e rl t ti5 1. k c o l c e c n e r e f e r z h m 5 . 8 4 1 s w o l l a , e v i t c a n e h w . w o l e v i t c a . k c o l c z h m 5 2 . 4 7 s w o l l a , e v i t c a n i n e h w t s e tl e v e l 3 l t t i6 1d l e h n e h w n o i t a r e p o p i h c l a m r o n . t s e t g n i r u t c a f u n a m r o f d e s u . w o l d n gd n u o r g, 3 2 , 8 1 , 6 1 3 n a e r a d n a , e c a f r u s e i d e h t o t d e t n u o m y l l a c i s y h p e r a s n i p d n u o r g , e c n a m r o f r e p l a m r e h t t s e b r o f . h t a p l a m r e h t e h t f o t r a p t n a t r o p m i g n i s u , e n a l p d n u o r g a o t d e t c e n n o c e b d l u o h s s n i p d n u o r g l l a . e l b i s s o p f i s a i v e l p i t l u m c c v, 5 2 , 1 2 , 7 6 2 . y l p p u s r e w o p v 3 . 3 + a c c vg o l a n a4 1 , 8 , 3. u r c e h t r o f y l p p u s r e w o p v 3 . 3 + g o l a n a a d n gg o l a n a3 1 , 9. u r c e h t r o f d n u o r g g o l a n a c n2 3 , 7 2 , 0 1. t c e n n o c o n table 1. pin assignment and description
4 hd-sdi data retimer S8301 december 8, 1998 / revision a figure 4. 32 tqfp pinout lockrefn gnd refclk vcc bpssp bpssn gnd lockdet gnda nc lpf2 lpf1 gnda vcca refsel test nc gnd sel altp altn nc vcc vcc datap datan vcca doutp doutn gnd vcc vcca 32 tqfp 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25
5 S8301 hd-sdi data retimer december 8, 1998 / revision a figure 5. 32 tqfp (7 x 7 x 1.4mm) package
6 hd-sdi data retimer S8301 december 8, 1998 / revision a s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us t n e m m o c t r t , f e m i t l l a f d n a e s i r k l c f e r7 . 1s n t fe c n a r e l o t y c n e u q e r f k l c f e r0 0 1m p p k l c f e r n e e w t e b e c n e r e f f i d y c n e u q e r f a t a d x r d n a c de l c y c y t u d k l c f e r0 40 6% t r s t , f s n / p t u o d0 7 2s p0 5 w ) % 0 8 - 0 2 ( v 0 . 2 - c c v o t t r s t , f s n / p s s p b0 7 2s p0 5 w ) % 0 8 - 0 2 ( v 0 . 2 - c c v o t t p o r p n / p s s p b o t n / p a t a d2s n s n o i t a c i f i c e p s r e t t i j t u o j rn / p t u o d ) s m r ( r e t t i j m o d n a r0 2s p t u o j dn / p t u o d ) p - p ( r e t t i j c i t s i n i m r e t e d0 0 1s p t j dn / p a t a d e c n a r e l o t r e t t i j t n e m n g i l a2 . 0i u k a e p - o t - k a e p . n r e t t a p 5 . 8 2 k / w r f x j o t t u p n i ( g n i k a e p r e f s n a r t r e t t i j ) t u p t u o 2 . 0b d h t i w z h m 1 . 2 t a . q e r f f f o t u c . n r e t t a p 0 1 0 1 t j te c n a r e l o t r e t t i j l a t o t0 . 1i u - f o - t u o r e t t i j t n e m n g i l a 5 . 8 2 k d n a b - n i r e t t i j , i u 2 . 0 d n a b . i u 8 . 0 table 3. ac characteristics table 2. performance summary r e t e m a r a p1 0 3 8 ss t i n u y c n e u q e r f g n i t a r e p o5 8 4 1s p b m d o i r e p k c o l c l a i r e s7 3 6 .s n e m i t n o i s i u q c a0 5 2s e m i t t i b k c o l c e c n e r e f e r5 2 . 4 7z h m
7 S8301 hd-sdi data retimer december 8, 1998 / revision a table 4. dc characteristics (over recommended operating conditions) s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c v h o ) l t t ( e g a t l o v h g i h t u p t u o2 . 2vi h o a m 1 . - = v l o ) l t t ( e g a t l o v w o l t u p t u o5 . 0vi l o a m 2 . 1 + = v h i ) l t t ( e g a t l o v h g i h t u p n i0 . 2c c vv v l i ) l t t ( e g a t l o v w o l t u p n i8 . 0v i h i ) l t t ( t n e r r u c h g i h t u p n i0 5a v n i v 4 . 2 = i l i ) l t t ( t n e r r u c w o l t u p n i0 0 5 -0 5 -a v n i v 5 . 0 = v c c e g a t l o v y l p p u s4 1 . 37 4 . 3vv c c % 5 v 3 . 3 = i c c t n e r r u c y l p p u s5 3 10 0 2a mv . n e p o s t u p t u o c c v = c c x a m p d n o i t a p i s s i d r e w o p5 .7 .w v . n e p o s t u p t u o c c v = c c x a m d v t u o l a i t n e r e f f i d t u p t u o l c e p v l g n i w s e g a t l o v k a e p - o t - k a e p 0 0 2 10 0 2 2v m p - p 0 5 w v o t c c v 0 . 2 - d v n i - o t - k a e p l a i t n e r e f f i d r e v i e c e r d n a x r , y t i v i t i s n e s t u p n i k a e p i s 0 0 20 0 6 2v m p - p v c c . d e l p u o c c a , v 3 . 3 = v o t d e s a i b c d y l l a n r e t n i c c v 5 6 . 0 -
8 hd-sdi data retimer S8301 december 8, 1998 / revision a notes: 1. caution: stresses listed under absolute maximum ratings may be applied to devices one at a time without causing permanent damage. functionality at or above the values listed is not implied. exposure to these values for extended periods may affect device reliability. 2. amcc guarantees the functional and parametric operation of the part under recommended operating conditions:" except where specifically noted in the ac and dc parametric tables. r e t e m a r a pn i mp y tx a ms t i n u v ( e g a t l o v y l p p u s r e w o p l t t c c )5 . 04v v ( , e g a t l o v t u p n i c d l c e p p n i )5 . 0 - v c c 5 . 0 + v v ( , e g a t l o v t u p n i c d l t t p n i )5 . 0 -5 . 5v h g i h r o f s t u p t u o o t d e i l p p a e g a t l o v c d v ( e t a t s t u p t u o n i , l t t ) 5 . 0 - v c c 5 . 0 + v i ( t n e r r u c t u p t u o l t t t u o ) h g i h t u p t u o , c d ( )0 5a m i ( t n e r r u c t u p t u o l c e p t u o ) h g i h t u p t u o , c d ( )0 5a m t ( s a i b r e d n u e r u t a r e p m e t e s a c c )? 5 5 -? 5 2 1c t ( e r u t a r e p m e t e g a r o t s g t s )? 5 6 -? 0 5 1c d s e t u p n i m u m i x a m ) 2 f p l d n a 1 f p l r o f t c e p x e ( 0 0 0 1v r e t e m a r a pn i mp y tx a ms t i n u v ( e g a t l o v y l p p u s r e w o p d d )1 . 3 +5 . 3v ) t ( e g n a r e r u t a r e p m e t g n i t a r e p o t n e i b m a? 0? 0 7c table 5. absolute maximum ratings table 6. recommended operating conditions
9 S8301 hd-sdi data retimer december 8, 1998 / revision a figure 6. serial output load figure 7. high speed differential inputs figure 8. pll loop bandwidth components figure 9. if altp/n or datap/n not used backplane 150 150 0.1 f 0.1 f 0.1 f 0.1 f v cc - 0.65v 0.1 f 50 50 10k vcc 4k lpf1 lpf2 2.2 f 27 27 altp or datap altn or datan 10k 10k vcc figure 10. reference clock biasing circuit ttl xtal refclk it is recommended that a 60-70mv dc offset be provided. it is recommended that a 148.5 or 74.25 mhz crystal be implemented.
10 hd-sdi data retimer S8301 december 8, 1998 / revision a amcc is a registered trademark of applied micro circuits corporation. copyright ? 1998 applied micro circuits corporation amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (619) 450-9333 ? (800) 755-2622 ? fax: (619) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1 example: S8301tfS8301 in a 32 tqfp package shipped in trays. ordering information e c i v e dr e w o p q r i a l l i t s a j 1 0 3 8 sw 2 5 .w / c ? 5 6 thermal information e d a r gr e v i e c e re g a k c a p e r u t a r e p m e t e d a r ge d a r g e d a r g e d a r ge d a r g g n i p p i h s n o i t a r u g i f n o cn o i t a r u g i f n o c n o i t a r u g i f n o c n o i t a r u g i f n o cn o i t a r u g i f n o c d e t a r g e t n i - s s t i u c r i c 1 0 3 8p f q t 2 3 = f tl a i c r e m m o c - cs y a r t = k n a l b x e d a r g x x x x r e b m u n t r a p x e g a k c a p x e d a r g e r u t a r e p m e t x n o i t a r u g i f n o c
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